Answer:
The maximum permissible propagation delay per flip flop stage is 100 n sec
Explanation:
1024 ripple counter has 10 J-K flip flops(210 = 1024).
So the total delay will be 10×x where x is the delay of each J-K flip flops.
The period of the clock pulse is 1× 10⁻⁶ s.
Now
10x <= 10⁻⁶ s
x <= 100 ns
x= 100 ns for prpoer operation.
pulse train with a frequency of 1 MHz is counted using a modulo-1024 ripple-counter built with J-K flip flops. For proper operation of the counter, the maximum permissible propagation delay per flip flop stage is 100 n sec.
